The present invention relates to a semiconductor apparatus having a chip size package of the type used for a high density assembly module and a multi-chip module.
Recently, in association with the trend toward miniaturization and high performance of electronic devices, high density packing, high densification, and an increase in the speed of processing are also required for the semiconductor devices used therein. In correspondence with this objective, as a semiconductor apparatus mounting method, packages have been developed from the pin insertion type to the surface mounting type in order to increase the mounting density, and from a DIP (dual inline package) to a QFP (quad flat package) or a PGA (pin grid array) so as to correspond to the multi-pin type.
However, in the QFP type, the connection lead wires from the mounting substrate are centralized only in the peripheral part of the package, and the lead wires themselves are thin and deformable, so that, as the number of pins increases, the mounting has become more difficult. In the PGA type, the terminals to be connected to the mounting substrate are long and thin and centralized extremely, so that speeding up of the processing is difficult on an electric characteristic basis, and, since it is of a pin insertion type, surface mounting is not available and the type is disadvantageous in high density assembly.
Recently, to solve these problems and realize a semiconductor apparatus which is capable of high speed, a BGA (ball grid array) package has been developed which has a stress cushioning layer between a semiconductor chip and a substrate with a wiring circuit formed thereon, and a bump electrode is provided as an external terminal on the mounting substrate surface side of the substrate (U.S. Pat. No. 5,148,265). In a package having this structure, the terminals to be connected to the mounting substrate are ball-shaped solder, so that the lead wires are free of deformation, unlike the QFP type, and the terminals are scattered over all of the mounting surface. Hence, the pitch between the terminals can be made longer and the surface mounting is easy. The bump electrode, which is an external terminal, is shorter than that of the PGA type, so that the inductance component is small and the signal speed is fast. Hence, the structure can provide for high speed operation.
Recently, in association with wide spread use of portable information terminals, miniaturization and high density assembly of a semiconductor apparatus are required. Therefore, recently, a CSP (chip scale package) having a package size almost equal to the size of the chip has been developed. In xe2x80x9cNikkei Microdevicexe2x80x9d (p. 38 to p. 64) issued by Nikkei BP, Ltd. (February 1998), various types of CSPs are disclosed. These CSPs are manufactured in such a way that semiconductor chips cut into pieces are adhered to a polyimide or ceramics substrate with a wiring layer formed thereon, and then the wiring layer and semiconductor chips are electrically connected by wire bonding, single point bonding, gang bonding, or bump bonding, and the connections are sealed with resin, and finally an external terminal, such as a solder bump is formed.
Japanese Patent Application Laid-open 9-232256 and Japanese Patent Application Laid-Open 10-27827 disclose methods for mass-producing CSPs. The methods form a bump on a semiconductor wafer, electrically connect a wiring substrate via the bump, then seal the connections with resin, form an external electrode on the wiring substrate, and finally cut it into pieces, in the manufacture of a semiconductor apparatus.
xe2x80x9cNikkei Microdevicexe2x80x9d (p. 164 to p. 167) issued by Nikkei BP, Ltd. (April 1998) discloses another method for mass-producing CSPs. The method forms a bump on a semiconductor wafer by plating, seals the part other than the bump with resin, forms an external electrode in the bump part, and then cuts it into pieces, in the manufactures of a semiconductor apparatus.
Japanese Patent Application Laid-open 10-92865 discloses a semiconductor apparatus of a type having a resin layer for cushioning the stress between an external electrode and semiconductor chips, in which chips are processed in units of wafers in a batch and then cut into pieces.
In the aforementioned semiconductor apparatuses of the type wherein, after resin layers and external electrodes are formed, in a batch, in units of semiconductor wafers and the wafers are then cut into pieces, the interfaces of the layers are always exposed on the end face of the package. Therefore, due to the thermal stress caused by sudden temperature changes at the time of mounting the package and the mechanical stress at the time of the dicing of the chips into pieces, the stress is centralized on the interfaces between the chips and the resin layers which are exposed at the end of the package, and peeling is generated from there, so that the package is damaged. As a result, the reliability of the semiconductor apparatus is reduced, and the manufacturing yield rate also is reduced.
The present invention, with the foregoing in view, provides a semiconductor apparatus of high reliability and a semiconductor apparatus manufacturing method having a high manufacturing yield rate for preventing stress concentration on interfaces and suppressing peeling-off between chips and resin layers when thermal stress and mechanical stress are applied to a package.
The aforementioned problems can be solved by the features indicated below. The following is a summary of the features of the present invention.
(1) In a semiconductor apparatus having, on the surface of a semiconductor chip having a circuit and an electrode formed thereon, a stress cushioning layer on a part other than where the electrode is formed, a wiring layer connected to the electrode on the stress cushioning layer, an external protection film on the wiring layer and stress cushioning layer, a window where a part of the wiring layer is exposed at a predetermined location of the external protection film, and an external electrode which is electrically connected to the wiring layer via the window, wherein the stress cushioning layer, wiring layer, conductor, external protection film, and external electrode are formed on the inside of the end of the semiconductor chip.
(2) In a semiconductor apparatus having, on the surface of a semiconductor chip having a circuit and an electrode formed thereon, a chip protection film on a part other than where the electrode is formed, a first wiring layer and a stress cushioning layer connected to the electrode on the chip protection film, a second wiring layer connected to the first wiring layer on the stress cushioning layer, an external protection film on the second wiring layer and stress cushioning layer, a window where a part of the wiring layer is exposed at a predetermined location of the external protection film, and an external electrode which is electrically connected to the wiring layer via the window, wherein the chip protection film, stress cushioning layer, wiring layer, external protection film, and external electrode are formed on the inside of the end of the semiconductor chip.
(3) A semiconductor apparatus manufacturing method having 1. a step of forming a stress cushioning layer on a circuit forming surface of a semiconductor wafer on which a plurality of semiconductor elements are formed, 2. a step of forming an opening for exposing the chip electrode on the stress cushioning layer on an electrode of the semiconductor wafer, 3. a step of forming a slit in the stress cushioning layer on a scribe line for cutting the semiconductor wafer, 4. a step of forming a wiring layer connected to the electrode of the semiconductor chip on the stress cushioning layer via the opening, 5. a step of forming an external protection film having a window for connecting an external electrode on the stress cushioning layer and wiring layer except for the scribe line, 6. a step of forming an external electrode, and 7. a step of cutting the semiconductor wafer in a minimum unit for semiconductor apparatuses obtained after cutting to operate.
A semiconductor apparatus manufacturing method, wherein, instead of Step 5, there is 5(a). a step of forming a window for connecting an external electrode and an external protection film having an end on the inside of the end of the stress cushioning layer on the stress cushioning layer and wiring layer, or 5(b). a step of forming a window for connecting an external electrode and an external protection film having an end between the scribe line and the end of the stress cushioning layer on the stress cushioning layer and wiring layer.
(4) A semiconductor apparatus manufacturing method having 1. a step of forming a chip protection film on a circuit forming surface except wherein there is an electrode of a semiconductor wafer on which a plurality of semiconductor elements are formed and a scribe line for cutting the semiconductor wafer, 2. a step of forming a first wiring layer electrically connected to the electrode on the chip protection film, 3. a step of forming a stress cushioning layer on the chip protection film and first wiring layer, 4. a step of forming an opening for exposing a part of the wiring layer on the stress cushioning layer, 5. a step of forming a slit in the stress cushioning layer on the scribe line, 6. a step of forming a second wiring layer connected to a part of the first wiring layer on the stress cushioning layer via the opening formed in the stress cushioning layer, 7. a step of forming an external protection film having a window for connecting an external electrode on the stress cushioning layer and wiring layer except the scribe line, 8. a step of forming an external electrode, and 9. a step of cutting the semiconductor wafer in a minimum unit for semiconductor apparatuses obtained after cutting to operate.
A semiconductor apparatus manufacturing method, wherein, instead of Step 7, there is 7(a). a step of forming a window for connecting an external electrode and an external protection film having an end on the inside of the end of the stress cushioning layer on the stress cushioning layer and second wiring layer.
A semiconductor apparatus manufacturing method, wherein, after Step 1 and Step 2 mentioned above, there is 3. a step of forming a stress cushioning layer having an end on the inside of the end of the chip protection film on the chip protection film and first wiring layer, 4. a step of forming an opening for exposing a part of the first wiring layer on the stress cushioning layer, 5. a step of forming a second wiring layer connected to a part of the first wiring layer on the stress cushioning layer via the opening formed in the stress cushioning layer, 6. a step of forming a window for connecting an external electrode and an external protection film having an end on the inside of the end of the stress cushioning layer on the stress cushioning layer and second wiring layer, 7. a step of forming an external electrode, and 8. a step of cutting the semiconductor wafer into minimum units for semiconductor apparatuses to operate.
A semiconductor apparatus manufacturing method, wherein, after Step 1 and Step 2 mentioned above, there is 3. a step of forming a stress cushioning layer on the chip protection film and first wiring layer, 4. a step of forming an opening for exposing a part of the wiring layer on the stress cushioning layer, 5. a step of forming a slit so that the end of the stress cushioning layer is formed between the scribe line and the end of the chip protection film, 6. a step of forming a second wiring layer connected to a part of the first wiring layer on the stress cushioning layer via the opening formed in the stress cushioning layer, 7. a step of forming a window for connecting an external electrode and an external protection film having an end on the inside of the end of the stress cushioning layer on the stress cushioning layer and second wiring layer, 8. a step of forming an external electrode, and 9. a step of cutting the semiconductor wafer into minimum units for semiconductor apparatuses to operate.
A semiconductor apparatus manufacturing method, wherein, after Step I and Step 2 mentioned above, there is 3. a step of forming a stress cushioning layer having an end on the inside of the end of the chip protection film on the chip protection film and first wiring layer, 4. a step of forming an opening for exposing a part of the first wiring layer on the stress cushioning layer, 5. a step of forming a second wiring layer connected to a part of the first wiring layer on the stress cushioning layer via the opening formed in the stress cushioning layer, 6. a step of forming a window for connecting an external electrode and an external protection film having an end on the same surface as that of the end of the chip protection film on the stress cushioning layer and second wiring layer, 7. a step of forming an external electrode, and 8. a step of cutting the semiconductor wafer into minimum units for semiconductor apparatuses to operate.
A semiconductor apparatus manufacturing method, wherein, after Step 1 and Step 2 mentioned above, there is 3. a step of forming a stress cushioning layer having an end on the inside of the end of the chip protection film on the chip protection film and first wiring layer, 4. a step of forming an opening for exposing a part of the first wiring layer on the stress cushioning layer, 5. a step of forming a second wiring layer connected to a part of the first wiring layer on the stress cushioning layer via the opening formed in the stress cushioning layer, 6. a step of forming a window for connecting an external electrode and an external protection film having an end between the end of the chip protection film and the end of the stress cushioning layer on the stress cushioning layer and second wiring layer, 7. a step of forming an external electrode, and 8. a step of cutting the semiconductor wafer into minimum units for semiconductor apparatuses to operate.
A semiconductor apparatus manufacturing method, wherein, after Step 1 and Step 2 mentioned above, there is 3. a step of forming a stress cushioning layer on the chip protection film and first wiring layer, 4. a step of forming an opening for exposing a part of the wiring layer on the stress cushioning layer, 5. a step of forming a stress cushioning layer having an end between the scribe line and the end of the chip protection film, 6. a step of forming a second wiring layer connected to a part of the first wiring layer on the stress cushioning layer via the opening formed in the stress cushioning layer, 7. a step of forming a window for connecting an external electrode and an external protection film having an end between the end of the stress cushioning layer and the scribe line on the stress cushioning layer and second wiring layer, 8. a step of forming an external electrode, and 9. a step of cutting the semiconductor wafer into minimum units for semiconductor apparatuses to operate.
On the surface of each of semiconductor chips of the present invention, a semiconductor circuit of logic, memory, and gate array formed by a predetermined process and an electrode for sending and receiving electric signals to and from the outside are formed.
The stress cushioning layer is preferably made of a low elastic resin. For example, fluororubber, silicone rubber, silicone rubber fluoride, acrylic rubber, hydrogenated nitride rubber, ethylene propylene rubber, chlorosulfonated polystyrene, epichlorohydrin rubber, butyl rubber, urethane rubber, polycarbonate (PC)/acrylonitride-butadiene-styrene (ABS) alloy, polysiloxane diemethyl terephthalate (PCT)/polyethylene terephthalate (PET) interpolybutylene terephthalate (PBT)/polycarbonate (PC) alloy, polytetrafluoroethylene (PTFE), florinated ethylen propylene (FEP), polyarylate, polyamide (PA)/acrylonitride-butadiene-styrene (ABS) alloy, modified epoxy, modified polyolef in, and siloxane modified polyamide may be used.
In addition, there are various thermoset resins, such as epoxy resin, unsaturated polyester resin, epoxy isocyanate resin, maleimide resin, maleimide epoxy resin, cyanide ester resin, cyanide ester epoxy resin, cyanide ester maleimide resin, phenolic resin, diallyl phthalate resin, urethane resin, cyanamide resin, and maleimide cyanamide resin; and, a material with two or more kinds of the aforementioned resins combined, or a material with an inorganic filler mixed, may be used. It is also possible to give photosensitivity to the aforementioned resins and control the shape of the stress cushioning layer by a predetermined exposure and development process.
According to the present invention, the end of the aforementioned stress cushioning layer is formed on the inside of the end of the semiconductor chip. By doing this, compared with the interfaces exposed on the same surface, the stress between the semiconductor chip and the stress cushioning layer can be dispersed in a wider area, so that the stress is not centralized. As a result, the semiconductor chip is not easily peeled off from the stress cushioning layer.
Using a stress cushioning layer in which the thickness and coefficient of elasticity at room temperature are changed, a semiconductor apparatus according to the present invention was produced by way of a trial and was mounted in a mounting substrate, and the mounting reliability within the range from xe2x88x9255xc2x0 C. to 125xc2x0 C. was evaluated. As a result, it was found that, assuming the thickness of the stress cushioning layer as t (xcexcm) and the coefficient of elasticity at room temperature as E (MPa), when the relationship between the thickness and the coefficient of elasticity satisfies the following formula (1):
log(t)xe2x89xa70.988 log(E)xe2x88x921.515xe2x80x83xe2x80x83(1)
the mounting reliability is satisfactory. In the same way, when the relationship between the thickness and the coefficient of elasticity does not satisfy the following formula (2):
log(t)xe2x89xa6xe2x88x921.063 log(E)+4.839xe2x80x83xe2x80x83(2)
it is found that when each semiconductor wafer is to be processed independently, a warp is generated, and at the patterning step of the wiring layer forming process, a gap is generated between the semiconductor wafer and the patterning mask, so that a patterning failure is caused. Therefore, when a stress cushioning layer satisfying the relationship between the formulas (1) and (2) is applied, the yielding rate in the wiring layer forming process is increased.
From the above results, it can ben seen that it is desirable for the thickness and coefficient of elasticity of the stress cushioning layer of the present invention to satisfy the relationship between the formulas (1) and (2).
As a chip protection film, polyimide is generally used. However, if film forming is possible, there is no special limit to the material. A material with photosensitivity given may also be used. This chip protection film is also formed so that the end of the chip protection film is positioned on the inside of the end of the semiconductor chip in the same way as with the stress cushioning layer.
The wiring layer is formed on the chip protection film and stress cushioning layer using a conductor, such as gold, copper, or aluminum.
In a conductor layer formed between the wiring layer and the semiconductor chip, an opening is formed by exposure, development, and etching using a laser, such as a Hexe2x80x94Ne laser, Ar laser, YAG laser, or carbonic acid gas laser or a photosensitive material. Thereafter, by a method for filling the opening with a conductive resin, wherein a conductive powder of carbon, graphite, gold, silver, copper, nickel, silver plated copper, or silver plated glass is mixed in a resin binder, such as epoxy resin, silicon resin, or polyimide resin, or a no-electric-field plating method, or a method for heat-depositing or sputter-depositing a metal, such as gold or copper in a vacuum, a conductive film is formed on the inner surface of the opening, and then a conductive layer is formed by electroplating.
Although there is no special limit to the external protection film, it is general to form a composition wherein an inorganic f iller is mixed in an organic compound, such as epoxy resin, polyimide resin, or polyamide resin, on the stress cushioning layer and wiring layer, except the connection part of the wiring layer and external electrode, by screen print. In this case, a material to which photosensitivity is given may be used. The external protection film, in the same way as with the aforementioned stress cushioning layer and chip protection film, is also formed so that the end of the external protection film is positioned on the inside of the end of the semiconductor chip.
The external electrode is a conductor for effecting electrical connection to a substrate on which a semiconductor apparatus is mounted; and, more specifically, it is a ball-shaped electrode of a solder alloy including tin, zinc, and lead, silver, copper, or gold, or any of them coated with gold. In addition, a terminal having a structure of an alloy with one or more of molybdenum, nickel, copper, platinum, and titanium combined or a multi-layer of two or more of them may be used.